High density memory arrays typically are arranged in rows and columns having a memory cell element at the points of intersection (between the row and column) whereby one of either the rows conductors layer or columns conductors layer is layered above the other and is formed using metal material. In so much as metal is considerably more conductive than a doped semiconductor material, it is the material of choice for both the rows and columns. However, manufacturing considerations come into play when using a metal material for the bottom conductors layer because forming the memory cell element (prior to forming the top conductors layer) typically utilizes factory equipment that can become contaminated by the presence of metal. One solution can be to have dedicated equipment that is frequently cleaned, but this equipment is expensive and such an approach can be economically impractical. Another solution, as mentioned above, is to use a material other than metal (e.g., doped semiconductor material) for the bottom conductors layer, but because of the higher resistivity of such materials, performance of the final device can be compromised. What is needed is a design that can use higher resistance semiconductor material for the bottom conductors layer that compensates for the degraded performance.